Minimizing defects during wafer processing will continue to be a critical path to attaining cost effective manufacturing of advanced semiconductor devices. Hard particles can block etch processes causing an electrical “open” or “short” in the circuit. Particles of lesser size and those falling on critical locations on a device may create perturbations in the active features' critical dimensions, producing adverse or fatal consequences during device operation.
The gate level defect maximum density requirements for 15 nm gate technology is expected to be approximately 0.01/cm**2 at 10 nm in size per the ITRS 2005 roadmap. No lithographic and etch process tool exists with these performance capabilities.
One source for hard particle defect generation in the imaging process is the post-apply bake process. In these processes, solvent-rich, polymer-containing, spun-on films are baked at temperatures close to and even well above the boiling point of the casting solvent used. Temperatures range from 80 to 250 C. The most common byproducts of the post-apply bake are volatile organic compounds (VOCs) and some amount of polymer or other hard material that deposits on the inside of the bake chamber. This hard material builds up and eventually sheds or peels off, creating particles with time, usually after about 4,000 to 15,000 wafers are processed. The degree of particle generation depends on chemistry and bake temperature. The bake plate lid is typically mounted directly above the production wafer, so what comes loose from the lid often falls onto the production wafer.
Current solutions to the problem of particles from the bake plate lid include cooling down the bake system, removing the bake plate lid and cleaning it in various chemicals, including by dunking it in a bath of solvent. After cleaning, the bake system must be reassembled and tested for process compliance. This cleaning process can take 4 to 6 hours, during which time the tool is unusable for manufacturing.
It is anticipated that more frequent cleaning of bake plate lids will be required to meet the future device defect maximum density requirements.